1. Field of the Invention
The present invention relates to a differential amplifier circuit, a CMOS inverter, a demodulator circuit for use in data transfer by means of pulse-width modulation process, and a sampling circuit for use in the demodulator circuit, all of which are used for data transfer within a semiconductor integrated circuit device and achieve high speed operation and low power consumption.
2. Description of the Background Art
FIG. 27 is a block diagram showing data buses for data transfer between a memory cell array which is one type of memories and an arithmetic and logic unit (referred to hereinafter as an ALU) which is one type of computing circuits in a semiconductor integrated circuit device. In FIG. 27, the reference numeral 401 designates a memory cell array; the reference characters MD.sub.01, MD.sub.02 to MD.sub.n1, MD.sub.n2 designate pairs of input/output lines for reading and writing data from and to the memory cell array; 402.sub.1 to 402.sub.n designate pre-amplifier circuits for amplifying data on the pairs of input/output lines MD.sub.01, MD.sub.02 to MD.sub.n1, MD.sub.n2, respectively; 403 designates data buses connected to the pre-amplifier circuits 402.sub.1 to 402.sub.n for transferring data from the memory cell array 401; and 410 designates an ALU receiving the data read from the memory cell array 401 to perform computations on the data.
For computations in the ALU 410 using the information stored in the memory cell array 401, the information is read from the memory cell array 401 through the pairs of input/output lines MD.sub.01 to MD.sub.n2 and is transferred to the ALU 410 through the data buses 403. Since signals are attenuated on the data buses 403 during data transfer, the pre-amplifier circuits 402.sub.1 to 402.sub.n just amplify the signals.
FIG. 28 is a circuit diagram of a differential amplifier circuit including a current mirror load as an example of the conventional pre-amplifier circuits. In FIG. 28, the reference numeral 411 designates a PMOS transistor having a source connected to a power supply 1 providing a voltage V.sub.DD, a gate and a drain; 412 designates a PMOS transistor having a gate connected to the gate of the PMOS transistor 411, a drain connected to the gate of the PMOS transistor 411, and a source connected to the power supply 1; 413 designates an NMOS transistor having a source connected to a power supply 2 providing a voltage V.sub.SS, a drain connected to the drain of the PMOS transistor 411, and a gate receiving an input voltage V.sub.I1 ; and 414 designates an NMOS transistor having a drain connected to the drain of the PMOS transistor 412, a source connected to the power supply 2, and a gate receiving an input voltage V.sub.I2.
Operation of the differential amplifier circuit of FIG. 28 is discussed with reference to the waveform charts of FIGS. 29A and 29B. The pre-amplifier circuit of FIG. 28 amplifies small-amplitude differential signals having the input voltages V.sub.I1 and V.sub.I2 to output an output voltage V.sub.O1. At time t.sub.100, since the input voltage V.sub.I1 is higher than the input voltage V.sub.I2, the NMOS transistor 413 flows a greater amount of current than the NMOS transistor 414. The output voltage V.sub.O1 is 0 V. However, since the input voltages V.sub.I1 and V.sub.I2 are both positive and higher than the threshold voltages of the NMOS transistors 413 and 414, currents i.sub.a and i.sub.b flow through the NMOS transistors 413 and 414 when the output voltage V.sub.O1 is stable at the high (voltage V.sub.DD) or low (voltage V.sub.SS) level.
At time t.sub.101 where the input voltage V.sub.I1 becomes a level equal to the input voltage V.sub.I2, the currents i.sub.a and i.sub.b flowing through the NMOS transistors 413 and 414 become equal. When the input voltage V.sub.I2 is higher than the input voltage V.sub.I1, for example, at time t.sub.102, the currents i.sub.a and i.sub.b flowing through the NMOS transistors 413 and 414 have values I.sub.L and I.sub.H, respectively. In this manner, more current flows through the NMOS transistor receiving the higher voltage at its gate and the current continues flowing after the output from the differential amplifier circuit is determined, resulting in a great amount of current consumption. However, the decrease in the direct current for reduction in current consumption reduces the driving capability of the differential amplifier circuit, resulting in low speed operation of the differential amplifier circuit.
As stated above, in the data transfer within the conventional single semiconductor integrated circuit device including a memory such as the memory cell array 401 and a functional block such as the ALU 410 for computing the data read from the memory, it is necessary to arrange the plurality of data buses 403 consisting of an increased number of signal lines within the semiconductor integrated circuit device in order to provide a higher data transfer rate between the memory cell array 401 and the ALU 410. The result is an increased number of pre-amplifier circuits 402.sub.1 to 402.sub.n connected to the data buses 403 and, accordingly, increased power consumption in the pre-amplifier circuits.
Further, the number of long data buses within the semiconductor integrated circuit device increases, resulting in increased layout area of the data buses in the semiconductor integrated circuit device and increased power consumption to drive the plurality of heavily loaded data buses. The data buses wired over relatively long distances between the memory cell array 401 and ALU 410 have large wiring capacitances, resulting in increased power consumption to drive the plurality of heavily loaded data buses.
Additionally, relatively large direct current continues flowing in the differential amplifier circuit during the time no output transition occurs, increasing the current consumption in the differential amplifier circuit.